1. Field of the Invention
The present invention relates generally to the field of circuits and more particularly to analog-to-digital converters.
2. Related Art
Advances in semiconductor manufacturing technologies have decreased the physical dimensions of the circuit and interconnect elements in integrated circuits. One consequence of these physical changes is the introduction of integrated circuits that operate at high speed, and that also include many functions on a single integrated circuit. The electrical and electronic systems made possible by these high-speed, high-function integrated circuits also require improved analog circuits to provide performance commensurate therewith. One exemplary class of such analog circuits is referred to as analog to digital converters. Some of these circuits include another class of analog circuit configuration referred to as switched capacitor circuits.
Analog to digital converters that use switched-capacitor analog circuits suffer from performance degradations such as reduced signal-to-noise ratio (SNR) and in-band spurious signals, because of the finite precision of the analog elements used to implement such circuits.
By way of illustration, switched capacitor circuits are used in the known delta-sigma analog-to-digital converter (ADC) that is implemented with multi-phased sample-and-hold (S/H) circuits and multi-phased resonators. Multi-phased S/H circuits may allow more time to complete the capture of an input signal than a single-phase S/H circuit. This eases the speed requirements on the S/H circuitry. Multi-phased resonators are used to implement band-pass delta-sigma ADC circuits. The elements within a multi-phased circuit are matched to prevent performance degradation.
FIG. 1a shows a conventional analog to digital converter having two main parts: a modulator 5 and a digital signal processing (filter) section 7. The modulator 5 accepts an analog input at its input terminal and applies it to a sample and hold circuit 10. Resonators 14 and quantizier 20 output a digital signal (word) to feedback digital to analog converter 22.
FIG. 1b shows in detail an example of a modulator 5 of the FIG. 1a ADC having a S/H circuit 10 followed by two second order band-pass resonators 14, 18. The combination of the resonators gives a fourth order response. Also included is a summer 16, N-bit quantizer 20, and N-bit DAC 22 connecting to feedback summer 12. In a conventional implementation the characteristics of the capacitors and switches within the S/H circuit are matched to each other to prevent performance degradation. It is known that imperfections and mismatches in analog components (switches and capacitors) result in undesirable noise and spurious products. Such imperfections include timing skews across switches, parasitic resistance and capacitance, and the absolute and relative linearity of the components. Likewise, in a conventional implementation the elements within the resonator are matched. It is noted that perfect matching of such analog components is difficult, if not impossible.
The consequences of imperfections and mismatched components in a conventional fourth order band-pass delta-sigma ADC, such as that shown in FIG. 1a, are shown in the spectra of FIGS. 2, 3, and 4, and are also summarized in Table 1.
FIG. 2 shows the spectrum at the output port of a modulator of a conventional delta-sigma ADC having a single-phase S/H circuit and a two-phase resonator. The spectrum contains noise and spurious signals resulting from 1% mismatches in the resonator capacitors. The center of the signal band is at a normalized frequency of 0.25, where the sampling frequency (Fs) equals 1. The signal band is bounded by the band-pass filter response which is ultimately applied in the digital signal processing output stage of the ADC. Noise and signals within the signal band degrade the ADC performance. Noise and signals outside the signal band are rejected by the band-pass filter and are typically not a concern. In this example, resonator capacitor mismatches create an in-band spurious signal and produce a limited amount of in-band noise. In-band noise in this example is tolerable, but the in-band spur is problematic.
FIG. 3 shows the spectrum at the output port of a modulator of a conventional delta-sigma ADC having a single-phase S/H and a three-phase resonator. The spectrum contains the noise and spurious signals resulting from 1% mismatches in the resonator capacitors. In this example, resonator capacitor mismatches create out-of-band spurious signals, but also produce excessive in-band noise. In this case, the out-of-band spurs are tolerable, but the in-band noise is problematic.
FIG. 4 shows the spectrum at the output port of a modulator of a conventional delta-sigma ADC having a two-phase S/H circuit and a three-phase resonator. A two-phase S/H circuit provides the benefit of operating the S/H circuit elements at half speed. The spectrum contains the noise and spurious signals resulting from 1% mismatches in the S/H circuit and resonator capacitors. S/H circuit capacitor mismatches create an in-band spurious signal, while resonator capacitor mismatches create out-of-band spurs together with excessive in-band noise. In this case, the out-of-band spurs may be tolerable, but the in-band spurs and noise are problematic.
Methods and apparatus are therefore needed for reducing in-band noise and spurs that are due to mismatches and imperfections in components.